NXP Semiconductors /MIMXRT1011 /CCM /CCGR1

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Interpret as CCGR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CG00CG10CG20CG30CG40CG50CG60CG70CG80CG90CG10 0CG11 0CG12 0CG13 0CG14 0CG15

Description

CCM Clock Gating Register 1

Fields

CG0

lpspi1 clocks (lpspi1_clk_enable)

CG1

lpspi2 clocks (lpspi2_clk_enable)

CG2

Reserved

CG3

Reserved

CG4

Reserved

CG5

Reserved

CG6

pit clocks (pit_clk_enable)

CG7

Reserved

CG8

adc1 clock (adc1_clk_enable)

CG9

Reserved

CG10

gpt1 bus clock (gpt_clk_enable)

CG11

gpt1 serial clock (gpt_serial_clk_enable)

CG12

lpuart4 clock (lpuart4_clk_enable)

CG13

gpio1 clock (gpio1_clk_enable)

CG14

csu clock (csu_clk_enable)

CG15

gpio5 clock (gpio5_clk_enable)

Links

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